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Integrated Circuit Design
Because of the financial and social impact of the electronics market,
trends in semiconductor design have been well documented. Similarly, there has
been a concerted effort by industry groups and government agencies to provide
projections regarding future integrated circuit designs. With regard to heat
dissipation, there are important market drivers toward both lower and higher
There are two key drivers toward lower dissipation values.
The first is a desire to avoid pushing dissipation to levels that will require
the use of non-traditional cooling schemes. Figure 1 contains dissipation and
power data for a number of different high-end processors, as well as data from
computational studies . As can be seen in the figure, the generally accepted
chip dissipation limit for forced convection cooling is in the vicinity of 1
1. Various published papers use this limit but
there is clearly a range in the design community's view. In systems where extremely
high reliability is required (e.g., military avionics systems), forced convection
cooling is used up to a limit of roughly 0.3 W/sq.cm. Conversely, there are
commercial forced-convection cooled systems where 2 W/sq.cm. chips are being
Figure 1: High-end processor dissipation and cooling
The second driver away from increased dissipation is a broad
push to reduce power consumption. This trend is driven by a broad array of forces
ranging from general DFE (Design For the Environment) strategies to the need
to reduce the restrictions that battery life puts on portable computing/communication
devices. For large scale electronic systems (e.g., telecom transmission and
switching facilities), reduced power consumption translates into operating cost
reductions which can be significant over the lifetime of the systems.
In opposition to these effects are a number of drivers which
are pushing chip dissipation levels up. The two most significant drivers are
the continued demand for higher throughput and for increased on-chip circuit
densities. Projections for clock speed and circuit density growth, as published
by the Semiconductor Industry Association (SIA), are shown in Figures 2 and
3.2. The clock speed data is specified for two categories of microprocessors:
"high" performance and "cost" performance.
2. The SIA report was composed with the support
of NIST; NSF; the Departments of Commerce, Defense and Energy; Semiconductor
Research Corporation and SEMATECH (an industry consortia); and various universities.)
Figure 2: Projected on-chip clock frequencies for "cost
performance" and "high performance" integrated circuits.
Figure 3: Projected transitor densities for high volume
?-processors and low volume ASICs.
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