Viewing page 3 of 3 pages.
Previous 1 2 3
NEHALEM / CORE i7
How this latest high end Intel CPU became Core i7 is just another marketing
tale. That it will maintain Intel's substantial performance lead over AMD is
clear. Information about Nehalem was scattered throughout IDF Fall 2008, and
with every demo and info snippet, the dominance of Intel in the x86 chip sector
seemed more assured.
There are numerous, highly detailed discussions about Core i7 architecture
elsewhere on the web, and rather than try to duplicate other tech writers fine
efforts, links to a sampling of such articles follow:
Inside
Nehalem by Daniel A. Begun - Hot Hardware - Mostly a walk-through
guide of an Intel slide presentation about Nehalem, but is worthwhile as an
introduction.
What
you need to know about Intel's Nehalem CPU by Jon Stokes - Ars Technica
- This is a succinct, well-written piece on the core features that the new
architecture will eventually bring to Intel's entire x86 processor line.
Nehalem
- Everything You Need to Know about Intel's New Architecture by Anandtech
- The usual everything including the kitchen sink analysis by Anand, who already
published a preview of Nehalem benchmarks during Computex a couple of months
earlier: The
Nehalem Preview: Intel Does It Again
Intel naturally has more than a few words about Core i7. They begin here, Next-Generation
Intel Microarchitecture, with a summary of key features:
* Dynamic scalability, managed cores, threads, cache, interfaces,
and power for energy-efficient performance on demand.
* Design and performance scalability for server, workstation, PC, and
mobile demands with support for 2-8+ cores and up to 16+ threads with simultaneous
multi-threading (SMT), and scalable cache sizes, system interconnects, and
integrated memory controllers.
* Simultaneous multi-threading brings high-performance applications
into mainstream computing with 1-16+ threads optimized for a new generation
multi-core processor architecture.
* Scalable shared memory of Intel QuickPath technology features memory
distributed to each processor with integrated memory controllers and high-speed
point-to-point interconnects to unleash the performance of next-generation
Intel® multi-core processors.
* Multi-level shared cache improves performance and efficiency by reducing
latency to frequently used data.
AMD fans have noted that Intel has finally done what should have been done
years ago: It has an integrated memory controller, a feature employed by AMD
for several years with the very first Athlon 64s. Note that the first Core i7s
will ship with a triple-channel DDR3 memory controller. This means that DDR3
DIMMs must be installed in sets of three to take advantage of the full memory
bandwidth. Later versions will ship with two active controllers, but the triple-channel
controller will be retained for high end and server CPUs.
This is only one of many features in Core i7 that require significant changes
from existing Intel platforms. Heatsink makers will be delighted about the change
to a new 1366 pin socket and larger CPU housing that require a bigger heatsink.
Existing heatsinks will probably not be adaptable to the new socket, making
possible a whole new round of heatsink sales to enthusiasts. The push-pin mounting
mechanism from LGA-775 is apparently being used with LGA1366, which is disappointing
for most hardware enthusiasts.
Some slides from a presentation by Stephen Thomas of the Intel Platform Applications
Engineering Division provide more details:
* * *
Discuss this article in the SPCR forums.
| Help support this site, buy from one of our affiliate retailers! |
|
