SPCR

AMD rolls out its 65-nanometer chips
Chips will consume about 30 percent less energy than the same chips produced on the 90-nanometer process when running at the same speed.


Advanced Micro Devices has started to ship chips made on the 65-nanometer process, as the manufacturing spat with Intel heats up.

AMD chips made on the 65-nanometer process will consume about 30 percent less energy than the same chips produced on the 90-nanometer process when running at the same speed. In the first chips shipped on this process, virtually all of the benefit comes in reduced power consumption, said Nick Kepler, vice president of logic technology development at AMD.

Later, the company will balance energy conservation and performance gain, depending on what the designers want to achieve with various desktop, notebook and server chip designs, he said.

The improvements in part come because AMD is straining the silicon in the transistors inside its chips with a silicon germanium film to improve performance, a first for the company.

Straining silicon improves the performance of transistors because the larger germanium atoms slightly rearrange the silicon atoms and thereby allow electrical carriers to move more rapidly. In the N-channel transistors, which carry negative electrons, germanium spreads out the lattice of the silicon; electrons flow more freely, sort of like a deer running through a forest that's been thinned of trees. In P-channel transistors, which carry positive charges, the germanium compresses the silicon atoms.

"We planned it (silicon germanium) all along with 65-nanometer, but we were prepared to pull the plug on it if it didn't add up to a benefit," Kepler said. "Adding embedded silicon germanium is probably the biggest change."

To create strain in its existing 90-nanometer chips, AMD (and IBM) inserted a technology called Dual Stress Liners, which is different straining the silicon germanium. Intel already uses silicon germanium extensively.

AMD's 65-nanometer chips will still include Dual Stress Liners, but also include silicon germanium on the P-channel transistors. The N-channel transistors, meanwhile, will get additional strain from something called Stress Memory Technology. With SMT, AMD inserts a film into the N-transistors and then eliminates it: although gone, the earlier existence changes the structure enough to create a strain. (AMD outlined these changes at a conference in 2005.)

SMT, Kepler added, is not a variant of another strain technique first discussed by IBM, which involves inserting and then evaporating the germanium layer.

The first chips produced by AMD on the new process will be desktop chips. Notebook and server chips will come in the relatively near future.

Intel and AMD are in the midst of a manufacturing battle. Intel first began shipping 65-nanometer chips in October 2005. Chips made on the 65-nanometer process generally provide more performance and/or consume less power than those made on the older 90-nanometer process. (The nanometer figure refers to the average size of features on the chip; a nanometer is a billionth of a meter).

Chips popped out on the more advanced processes also cost less to produce. Intel's 14-month lead in manufacturing has been one of the primary reasons it has been able to undercut AMD in some segments.

By moving into production with its first 65-nanometer chips, AMD can now start to try to erode that advantage. By the middle of next year, all of the chips coming out of AMD's Fab 36 in Dresden, Germany, (one of the two fabs AMD has there) will be only 65-nanometer chips.

Kepler also reiterated the company's goal of shipping chips on the 45-nanometer process in 18 months, a shorter than normal time period between manufacturing nodes. If successful, this will cut Intel's manufacturing advantage to about six to seven months.

But it won't be easy to do. The 45-nanometer transition is expected to be more complex than the 65-nanometer transition. Both AMD and IBM are committed to adopting immersion lithography--a technique where the silicon wafer is immersed in purified water to better focus the light beams that "draw" circuits on its surface--for 45-nanometer manufacturing. No one has moved into mass manufacturing with this technique yet. Intel will not adopt it for 45-nanometer manufacturing.

"Eighteen months to 45nm is tough but doable," wrote Risto Puhakka, an analyst at VLSI Research in an email. "Intel is concerned about the maturity of immersion lithography in their roadmaps...AMD is ramping 45nm later, which gives immersion time to mature, so in that sense the immersion is easier to choose."

While AMD is now one of the premier manufacturing outfits in the world, it still sometimes hits delays. The company shipped its first 90-nanometer chips in August 2004. Thus, the 90- to 65-nanometer jump took 28 months. Some analysts expected AMD to come out with 65-nanometer chips toward the middle of 2006.

The complex 130- to 90-nanometer jump took even more time. AMD was originally supposed to come out with 90-nanometer chips at the end of 2003. Intel had delays too, but has kept closer to the two-year timetable for transitions outlined by Moore's Law.

One thing that could make the transition to 45-nanometers easier for both companies is that the transition won't likely be as radical as it could have been. At one time, both AMD and Intel contemplated doing things like coming out with multiple gate transistors and changing the basic materials in their transistors at 45-nanometer. Now these changes will wait until further transitions.

AMD chips made on the 65-nanometer process will consume about 30 percent less energy than the same chips produced on the 90-nanometer process

andyb wrote:AMD and Intel chips both have a sliding scale for power usage, but they throw every chip "core disign" into the same bracket, which is plain wrong, a 2800+ Sempron thats rated at 62W will use much less than that, and I doubt that the top of the line Sempron actually uses 62W anyway.

dragmor wrote:I'm more interested in the claim that idle has drop from 7w to 3w.

C2D is said to be 14.3W on idle

jaganath wrote:

C2D is said to be 14.3W on idle

Xbitlabs measured 26W at idle, EIST enabled:

http://www.xbitlabs.com/articles/cpu/di ... ent_6.html

jaganath wrote:So what's going on? From the C2D shootout, apparently the highest-clocked chip (X6800) has a lower idle power than the E6300! That can't be right surely?

jaganath wrote:Wow, I gotta have me one of those! I was going to buy an X2 but I'll probably wait now til the 65nm parts are available.

jaganath wrote:I assumed the 65nm parts will see a 30% reduction across the board; so the standard 65nm X2 will use less than the 90nm, the "65W" version of the 65nm will use less (say 45W) and the EESFF 65nm will use less than the 90nm EESFF; tell me if that's not a correct assumption.

If anything the 90nm version gives you a slightly larger core to extract the heat from.

jaganath wrote:It also gives you more heat that needs to be extracted, so no net advantage.

Four Brisbanes are expected at launch: the Athlon 64 X2 4000+, 4400+, 4800+ and 5000+, clocked at 2.1GHz, 2.3Ghz, 2.5GHz and 2.6GHz, respectively. They're all TDP-rated at 65W and contain 1MB of L2 cache.

I assumed the 65nm parts will see a 30% reduction across the board; so the standard 65nm X2 will use less than the 90nm, the "65W" version of the 65nm will use less (say 45W) and the EESFF 65nm will use less than the 90nm EESFF; tell me if that's not a correct assumption.

Mats wrote: And, Xbitlabs measured 26W at idle, EIST disabled:

The 3800+ X2 65W can be had for $130 today

jaganath wrote:

The 3800+ X2 65W can be had for $130 today

Dang, the normal X2 is more like $180 in the UK; God I hate our ripoff prices!!

aristide1 wrote:

jaganath wrote:

The 3800+ X2 65W can be had for $130 today

Dang, the normal X2 is more like $180 in the UK; God I hate our ripoff prices!!

No price difference here.

Don't get upset, we just hide our taxes better than you guys.