Sorry to bump up this thread as well.
It'd be nice if you had documentation or proof for the ECC support of the consumer dual-cores. That they take ECC RAM doesn't mean the controller makes use of it.
Agreed. I saw things like this
, and then questioned specifically whether i3 + ecc memory would simply boot but not use ecc functionality, or whether it would actually detect and correct ECC errors. I was told it would correct ECC errors but unfortunately I cannot share my sources for this - although I trust them for technical accuracy. Added to this the S1200BT requires ECC memory, even with i3, otherwise it won't boot. From the tech specs
: "Only ECC memory is supported on this platform."
I have yet to find a utility which can tell me whether ECC mode is enabled on a live running system. If you can point me to such a utility, I'd be more than happy to run it on a C200 series based board with Core i3 (quite curious myself to see whether what I was told is true!).
Bear in mind though I only received this confirmation for Core i3 21xx, not for the pentium you refered to.
Just done some more digging and ran into this
, which is interesting even though it talks of mobile products.
I've been looking at building a small ECC capable FreeNAS box. After some looking around, I went with a Pentium G620 + S1200KP + 2x4GB unbuffered ECC RAM. The CPU choice was based on the understanding that it did in fact support ECC (IIRC, this was "confirmed" by a local sales rep to my supplier, but apparently the rep didn't want to commit too clearly on the matter).
I recently got the parts and put it together, and Memtest86+ apparently has some limited ability to read if the system is using ECC or not. In my case Memtest86+ reported ECC was off, and I could not turn it on. (There's also no RAM options in the motherboard BIOS.) After some digging around, I found that the Linux command line dmidecode can be used to report system properties, and on my system it reports:
Error Correction Type: Multi-bit ECC
Although it also reports that L1, L2 and L3 cache do *not* use ECC. Some of the sample output from dmidecode that can be found on the internet indicates that higher end Intel CPUs have single bit ECC there.
I'm now a little stuck. For one, not only is the output from Memtest86+ and dmidecode contradictory, but I've also seen notes that their output shouldn't be taken as absolute fact. Also, there's the issue of whether the G620 (and i3s) actually perform error correction, or they simply "support" the usage of ECC RAM.