is an interesting thread about why SSE is the default for Intel chips and not-enabled for Athlons. In short, it says that all cores after Palomino are subject to lockups with SSE enabled when processing Gromacs cores. Ironically, Palomino is the one core with no reported problems of lockups with SSE enabled.
In other words, if you have a Palomino core, definitely DO enable the assembly optomizations with -forceasm. If you have a T-bred or Barton, it might be OK and you might experience the odd lockup.
Supposedly nobody (at the Panda group anyway) has been able to reliably reproduce the problem, so it is not known whether the error is in the Athlon processors or in the Gromacs core. The workaround is that SSE is simply disabled by default on all Athlons.
What I took away from the above thread is that if you enable SSE, and you do not experience lockups, count yourself lucky and leave it enabled. If you experience lockups, the only reliable solution is to remove -forceasm or -forceSSE.
Keep in mind though, it's a 14 page thread and I did only skim the last page, so feel free to disagree with my conclusions.
I wonder though, how widespread is this problem? How many Athlon CPU's does it affect? 1 in 10? 1 in 10-thousand? I have no idea. This is just one thread, and maybe only a handful of people in the entire world have ever had trouble, but have made a big bruhaha about it. It does make me think back to why I put my Athlon and VIA chipset board on the shelf in favor of an Intel solution - I got tired of these weird and niggling little incompatibilities. So now I am considering Athlon/VIA again, and I wonder if I am repeating past mistakes.