Intel announcement on 22nm node and Ivy Bridge implications

[CA_Steve]

EE Times article.

Tri-gate 3D transistors. woo.

This line was my favorite:
"Alternatively, the new transistors consume less than half the power when at the same performance as 2-D planar transistors on 32-nm chips."

That should bring some serious smackdown to Ivy Bridge TDP's. It should also solve a good bit of the current SNB laptop thermal/noise issues.

[ces]

Sandy Bridge idles around 4 watts. You can't go below 0 watts.

Most of the energy is being used by the support chips. They real energy usage impact is going to occur when the support chips get this technology.

This will make it easier to shoe horn in 3 core chips into tight thermal situations where the concern is handing brief, infrequent... but still possible heavy computing loads.

It makes it safer to use less cooling (and PicoPSUs) with the same amount of peak horsepower.

[cordis]

Well, finally. Different foundries have been talking about FinFets for a long time, I'm glad Intel took the initiative and did it. This should spur the other foundries to start looking into it sooner, so that's a plus. I wonder if going to 8 cores in the same power envelope is what's pushing the process here. Ivy bridge is supposed to support 6 and 8 cores (12 and 16 with HT), if they want to support the same kind of speeds and yield that they get with the 1366 processors it may be where they're hitting the wall. I'll be very interested to see what kind of performance those processors wind up having.

[CA_Steve]

I think you are a little off topic, CES.

On topic: Reduction in load power.

On Topic: Other benefits of the 22nm node and the general coolness factor of the FinFETS.

Cordis - some speculation that this process will also enable Intel to better pursue mobile applications.

[cordis]

Well sure, it'll let them do better low power processors. Check out the graph on the Anandtech article here (http://www.anandtech.com/show/4313/inte ... in-2h-2011) for gate delay vs. operating voltage. You can see that it lets them drop 0.2v off the operating voltage to keep the same speed. Since dynamic power is proportional to the square of the voltage, any operating voltage drop can be very significant. Even better for mobile applications is the lower leakage power, for anything mobile you need to keep standby power low, and leakage is pretty critical for that. The only real hangup with it is that the extra steps in the new process will add more cost. That may be why they're starting in cpus, where they can charge whatever they want and work out any yield issues, and use it drive down costs.

[ces]

I think you are a little off topic, CES.
On topic: Reduction in load power.
On Topic: Other benefits of the 22nm node and the general coolness factor of the FinFETS.
Cordis - some speculation that this process will also enable Intel to better pursue mobile applications.

1. No problem we can carry on the conversation here where anything related to 3D transistors, power or performance is fair game:
viewtopic.php?f=28&t=62186

2. My apologies. My wandering off topic was not intentional. I thought I was in good faith sticking to the scope of your original post (see below).

EE Times article. Tri-gate 3D transistors. woo. This line was my favorite: "Alternatively, the new transistors consume less than half the Power when at the same Performance as 2-D planar transistors on 32-nm chips." That should bring some serious smackdown to Ivy Bridge TDP's. It should also solve a good bit of the current SNB laptop thermal/noise issues.

It is your thread... I am be pleased to conform to whatever scope you want... even if you want to change it. Could you explain what you want to be considered off topic in this thread.

Thanks

[CA_Steve]

The only real hangup with it is that the extra steps in the new process will add more cost. That may be why they're starting in cpus, where they can charge whatever they want and work out any yield issues, and use it drive down costs.

Intel slides are claiming only a 2-3% adder over alternative processes. But yeah, start with IvyBridge to work out the kinks.

[Olle P]

This new design and process could explain why the leaked info about Ivy Bridge shows TDPs roughly halved compared to Sandy Bridge. (45W typical for Ivy Bridge compared to 95W typical for Sandy Bridge.)

Seems like a win for just about everybody!

[cordis]

I've been thinking about this more, and there's another sector where this will pay off a lot. Servers and data centers are going to see a big payoff with these chips. Lowering the power for the same or higher performance on these is going to give them a huge advantage in server centers, clusters and other high performance systems. The power savings that data centers are going to have when they upgrade to these will be enormous. Intel is really going to clean up on server upgrades if they can keep the yield up. That may give them another reason not to charge into the mobile space immediately. Putting out the Ivy bridge chips, and I'm sure some Xeons too, will give them a chance to make the most money they can in the server market, before they put the technology into the commodity driven mobile space.